1. Field of the Invention
The present invention relates to switching of data packets in a FIFO-less non-blocking network switch configured for switching data packets between subnetworks.
2. Background Art
Local area networks use a network cable or other media to link stations on the network. Each local area network architecture uses a media access control (MAC) enabling network interface devices at each network node to access the network medium.
The Ethernet protocol IEEE 802.3 has evolved to specify a half-duplex media access mechanism and a full-duplex media access mechanism for transmission of data packets. The full-duplex media access mechanism provides a two-way, point-to-point communication link between two network elements, for example between a network node and a switched hub.
Switched local area networks are encountering increasing demands for higher speed connectivity, more flexible switching performance, and the ability to accommodate more complex network architectures. For example, commonly-assigned U.S. Pat. No. 5,953,335 discloses a network switch configured for switching layer 2 type Ethernet (IEEE 802.3) data packets between different network nodes; a received data packet may include a VLAN (virtual LAN) tagged frame according to IEEE 802.1 q protocol that specifies another subnetwork (via a router) or a prescribed group of stations. Since the switching occurs at the layer 2 level, a router is typically necessary to transfer the data packet between subnetworks.
Efforts to enhance the switching performance of a network switch to include layer 3 (e.g., Internet protocol) processing may suffer serious drawbacks, as current layer 2 switches preferably are configured for operating in a non-blocking mode, where data packets can be output from the switch at the same rate that the data packets are received. Newer designs are needed to ensure that higher speed switches can provide both layer 2 switching and layer 3 switching capabilities for faster speed networks such as 100 Mbps or gigabit networks.
One consideration in developing a network switch operating in a non-blocking mode is to include buffers in the design of the network switch. However, in switching layer 2 and layer 3 data packets, the size of buffers may be as large as 1500 bytes to match wire rates. Coupled with the fact that buffers occupy a proportionally larger amount of space on the wafer chip as compared to other components of the network switch, the use of buffers to match wire rates increases the overall cost of the network switch by increasing the overall size of the wafer chip.
There is a need for an arrangement that enables a network switch to provide layer 2 switching and layer 3 switching capabilities for 100 Mbps and gigabit links without blocking of the data packets.
There is also a need for an arrangement that enables a network switch to provide layer 2 switching and layer 3 switching capabilities with minimal buffering within the network switch that may otherwise affect latency of switched data packets or the size of the network switch.
There is also a need for an arrangement to provide layer 2 switching and layer 3 switching capabilities at a minimal cost within the network switch while maintaining non-blocking of the data packets.
There is also a need for an arrangement to provide layer 2 switching and layer 3 switching capabilities without buffering to lower the cost of the network switch.
There is also a need for an arrangement to enable a network switch port to instantaneously evaluate an incoming data packet and determine a layer 3 or higher protocol, to provide the associated switch fabric with sufficient time to process the incoming data packet according to the detected protocol.
These and other needs are attained by the present invention, where a network switch port filter is configured for evaluating an incoming data packet. The network switch port filter includes a min term memory configured for storing min term values of a plurality of equations. Each min term value specifying a prescribed value for comparison with a corresponding selected byte of the incoming data packet where each equation is identified by a corresponding equation identifier. The network switch port filter also includes a corresponding min term generator configured for simultaneously comparing a received byte of the incoming data packet with the min terms that correspond to the received byte and generating respective min term comparison results. The network switch port filter further includes a plurality of equation core modules. Each core module is configured for simultaneously generating a corresponding frame tag based on a corresponding equation identifier for a corresponding selected equation and the min term comparison results. Since a given received byte of the incoming data packet is simultaneously compared with the all the relevant min terms, this ensures the real time evaluation of the incoming data packet. Moreover, a plurality of equation core modules minimizes the need for a buffer because of the simultaneous generation of multiple frame tags minimizes latency in switching of the incoming data packet.
One aspect of the present invention provides a method of evaluating an incoming data packet at a network switch port. The method includes storing min term values of a plurality of equations in a min term memory. Each min term value specifies a prescribed value for comparison with a corresponding selected byte of the incoming data packet where each equation is identified by a corresponding equation identifier. The method also includes simultaneously comparing a received byte of the incoming data packet with min terms that correspond to the received byte and generating min term comparison results with a min term generator. The method further includes simultaneously generating a plurality of frame tags from a plurality of equation core modules. Each equation core module is configured for simultaneously generating a corresponding frame tag based on a corresponding equation identifier for a corresponding selected equation and the min term comparison results. The simultaneous comparisons of min terms and multiple equation core modules ensures that the incoming data packet may be evaluated in real time, reducing a need for buffering of incoming data packets, hence reducing the overall cost of the network switch port.
Additional advantages and novel features of the invention will be set forth in part in the description which follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The advantages of the present invention may be realized and attained by means of instrumentalities and combinations particularly pointed in the appended claims.